C, Vcs, Jtag, Perl, Verilog, Python, Tcl, Verdi, MBIST, gate-level simulation, DFT micro-architecture, Timing Constraints, EDA Tools, Synopsys Tetramax, Scan, Mentor Tessent

Perl, Verilog, Python, Tcl, Pre-Silicon test planning, low power concepts, RTL design for DFT, MBIST, DFT methodologies, systemverilog, Siemens Mentor Tessent, DFT Compiler, ATPG, Synopsys TetraMAX, DFT Integration Verification, Scan, Memory Repair, IJTAG

MBIST implementation and validation, RTL Coding, DFT insertion, ATPG, memory fault modeling and repair flows

Jtag, Tcl Scripting, Sta, Insertion verification on RTL Netlist level, Test point insertion, Test structures for DFT IP Integration, SDF based simulations for DFT modes, Scan insertion techniques, Memory BIST generation, Mentor Synopsys tools, MBIST, Post-Si ramp up and debug on ATE, Coverage improvement techniques, Fault Models, Test mode timing constraints, Industry standard Tools for Scan insertion, Physical Design, Gate level simulations, JTAG for IEEE1149.1 6 standards, ATPG, Scan

MemoryBIST, Fault Models, Tessent, ATPG, agentic AI flows, SDC constraint development, ATE test development, DFT timing closure, Tempus, TestKompress

test mode timing constraints definition, DFT concepts, Scan Insertion, Transition delay test coverage analysis, equivalence check DFT DRC rules, simulating test vectors, ATPG coverage analysis, Synopsys TetraMax, Genus, Cadence Encounter Test, DFTMax, ASIC DFT, timing fixes

Shell, Logic Design, Tcl, Python, Perl, Cadence, MBIST OCC validation flows, Synopsys, IEEE 1687 IJTAG standards, Scan insertion and ATPG tools, Digital Circuit Design, Hierarchical DFT and SDC constraint management, SpyGlass DFT rules, Mentor, Sta, SSN design, Physical design flows, Debug, RTL design synthesis