Project description

Product can be summarized as an advance bus traffic analysis solution, with very high speed compliance for modern protocols, based on a hybrid architecture of CPU and GPU processing, for a Global Networking Testing and Validation equipment provider. This is a state-of-the-art tool in product benchmarking adhering to the latest PCIe standards on the market.

Our team: A team of networking enthusiasts willing to contribute to customer success. Technologies used: Networking protocols, traffic generation tools, Windows/Linux servers, network virtualization, network security, wireless, network management tools, microservices

Opportunities: Networking and testing certifications, collaboration with an international team of professionals, working with the latest networking technologies and concepts, access to trainings

Responsibilities

Work closely with development engineering, product management, and customer solution engineering team to implement features functionality and system profiles for proprietary client application.
Collaborate with development team in view of integrating application components
Debug and troubleshoot complex issues and work closely with the engineering team on the failures and validate the fixes
Finding and alleviating architectural bottlenecks, providing solutions that truly help our customers achieving the same.
Review customer deployments, and customer found issues and address any gaps in production application blueprints

Mandatory Skills

Overall C/C++ background 5+ years , version 14+ preferred ; minimum developer experience 8+ years
Proven experience with PCIe Gen 5 and 6, CXL 2.0 and 3.0, as well as IDE (as specified by PCIe and CXL standards).
Low-level C++ programming. Bit/Byte manipulations.
Python 3.x experience is required, given some parts of the dev env will require various framework usage (harnesses)
Experience with state machine implementation.
Experience with data stream i/o processing use cases.
Understanding of network protocol stack.
Support software engineers with experimental software releases for unit testing as necessary.
Engaging in all phases of project development and design change, including concept, documentation, design reviews, prototype and test.
Write code that meets standards and delivers the desired functionality using the technology selected for the project.
Facilitate design reviews, define interfaces between code modules, and applies existing technology to designs.
Agile delivery experience with distributed teams.
Experience in performance, scale and convergence performance analysis of related issues and improving the findings at the system level.
Strong verbal and written communication skills. Ability to communicate effectively at all levels of the organization: Product Management, Technical Marketing, Field Sales, Documentation and Development Team.
Highly motivated and self-driven.
Able to collaborate cross-functionally to meet challenging goals.

Nice-to-Have Skills

Decode and understand PCIe and CXL packets/flits as captured by analyzer to write analysis code and to be able to write CXL compliance tests.
Sample of tasks usually performed on this project.
Participate in and decode DOE IDE Key Exchange.
Participate in and decode SMBus IDE Key Exchange.
SW - on-the-fly decryption of IDE TLPs in analyzer to enable trigger/filter on encrypted TLP contents.
Create and maintain the build plans for components/services.

Senior C++ Developer with PCIe Expertise