Lsf, Machine Learning, Neural Networks, Shell, Perl, Verilog, Python, System Verilog, Tcl, Sta, Rtl Design, Synthesis, constraints development

Vcs, Gdb, micro architecture definition, RTL coding using Verilog, scripting knowledge, Simulation Tools, Synthesis, interconnect design, LINT, debug tools like Debussy, design and verification tools, cache controller design

Verilog, ASIC design flow, Rtl Design, floor-planning, Eco, VCS or equivalent simulation tools, debug tools like Debussy GDB, Timing Analysis, scripting knowledge Python Perl shell, bring-up lab debug

C, Vcs, Perl, Verilog, Hardware Emulation Platforms, cdc, ASIC SoC development cycle, systemverilog, Rtl Design, spyglass, EVE, Veloce, ASIC Design, formal verification