Verilog, Static Timing Analysis, System Verilog, Spyglass CDC, Glitch analysis, SDC development

boundary scan , static timing analysis, Vcs, Verilog, Python, Perl, Tcl, Scan Insertion, sdf debugging, DFT CAD development, Jtag protocols, DFT logic IP integration, p1687, p1500, EDA Tools, BIST architectures, Test Architecture Methodology, Infrastructure, memory BIST, TetraMax, Functional Verification, Tessent, Gate level simulation, ATPG, Timing Closure, timing based simulations, TestMax