Verilog, Static Timing Analysis, System Verilog, Spyglass CDC, Glitch analysis, SDC development

Tcp, Pcie, Ethernet, System Verilog, Forwarding logic Parsers P4, RDMA, Building test benches, Palladium, Zebu, Veloce, ASIC verification using UVM, HAPS, formal verification

Networking Protocols, spyglass, Verilog RTL coding, Verplex LEC, high-speed serial interfaces, Synopsys Design Compiler, ASIC Design, multi-domain clock synchronization, high performance memory subsystems, ASIC debugging

SDF, LINT, Sta, Dft, Synthesis, cdc, primetime, MMMC, Tempus, GLS

Verilog, Python, Perl, Gdb, SOC design, Indago, Cadence