Perl, Python, Tcl, Clock domain partitioning, Power integrity and power-aware physical implementation, Block and subsystem-level physical design flows, primetime, Fusion Compiler, Clock gating, Congestion analysis and resolution, Clock tree architecture, Tempus, Cadence Innovus, Skew management, Certus, Synopsys ICC2, Timing closure and constraint management

Perl, Python, Tcl, VPlan, Synopsys VCS, Synopsys VC Formal, JasperGold, Cadence simulation tools, AMBA protocols, Uvm, systemverilog

synopsys primetime , Tcl, Python, Perl, SI noise analysis, AOCV, MMMC methodologies, timing exceptions, POCV, OCV, clocking methodologies

Azure - AKS, Python, Sql, Github, Docker, Arm

arm architecture , Usb, DDR, Perl, Pcie, Test Plan, Scripting, Python, Shell Programming, Tcl, Arm core, GIC, SMMU, Dms, verification checks, Arm system IP, verification plan, debug methodology, SoC Verification

monte carlo , python, AI ML, Cadence Virtuoso, Spice Simulator

rtl development , Cadence Palladium, scripting and programming skills, Synopsys HAPS platforms, Synopsys ZeBu, FPGA design methodologies