Uart, Spi, Gpio, Verilog, I2c, Arm, System Verilog, ASIC design flow, Interconnect fabrics, Cadence, Peripheral interface IPs, Arteris fabrics, System Verilog assertions, Axi, Scripting in Perl, APB, RTL Coding, Third-party IP integration, QSPI, I3C, Synopsys, USB standards, NoC architecture

firmware interaction, AMs, Cadence, Mentor, Uvm, systemverilog, Register models, industry VIPs, Avery, SERDES, link training, Siemens, Synopsys, Calibration

synopsys primetime , Synopsys FusionCompiler, AI ML Integration, Advanced Node Experience, Timing Signoff Tools, Physical Design Flow, SDC Proficiency, Advanced Clocking

Jenkins, Github, Git, Pytest, C, Verilog, Python, System Verilog, Git actions

Industry standard protocols, Gate level simulations, Power aware simulations, ARM based SoC verification, ASIC verification concepts