C, Uart, Spi, Shell, Verilog, Ethernet, I2c, Python, Systemc, Tcl, SVI3, systemverilog, Axi, formal verification, DMA, UVM-based testbench development, AHB, power-aware verification UPF, NoC bus and interconnect verification

Debugging test pattern issues, Scan Insertion, DFT implementation, Programming or scripting, ATPG, DFT RTL insertion, SRAM repair, MBIST, DFT methodology, LBIST

ASIC design flows, Verilog Coding, Digital IC design methodologies, Logic Synthesis, Timing Analysis

Jtag, System Verilog, Static timing analysis, DFT techniques, IEEE 1500 Standard, Commercial test generation tools, Logic diagnosis, Yield learning, Synopsys DFT Max, Tetramax tools, Verification UVM methodology, Mentor Tessent, IEEE 1687 standard, ATPG test pattern translation, ATPG tools, Scan insertion tools, Chip design Verilog, MBIST, Familiarity with ATE, Scripting Perl, Scan compression, Test compression software, Gate-level simulations, LBIST

Soc, Static Timing Analysis, Digital Circuits

automation, Ovm, Tcl Scripting, Verilog, Perl, test-bench development, GLS, Uvm, RTL, SV, SDF sim debug, Specman, HVL, functional and code coverages, closure constraint randomization, assertions development, eRM methodology, formal verification

Tcl, FPGA Design, System Verilog, C, Python, Unix Shell Script, Perl, Vcs, Synthesis, RTL validation, LINT, Synopsys simulators

Verilog Coding, Logic Synthesis, Digital IC design methodologies, Timing Analysis, ASIC design flows