Unix, Shell, Perl, Linux, Verilog, Python, Uvm, systemverilog

Uml, Java, Python, Algorithms, Data structures, Oop, Eclipse

Asic verification, digital design verification, Uvm, test bench architecture, systemverilog, GIT version control, functional coverage, C Language

System Verilog, Python, Emulation, Uvm, Palladium, AMBA

Arm, C, Python, Perl, Uvm, vManager, RISC-V Assembly, Cadence SKILL, systemverilog, Mixed Signal chips