Verilog, Usb, Tcl, Ethernet, Git, Ecos, C, Perforce, Python, Pcie, DDR, Xilinx Vivado, systemverilog, Cadence, static RTL checks, Synthesis, Axi, FPGA design tools, Mentor simulation suites, Intel Quartus, AMBA bus protocols, low power design techniques, Rtl Design, Lattice Diamond, STA timing closure, SoC architectures

Usb, Verilog, Ethernet, Pcie, DDR, Synthesis, FPGA design tools, Intel Quartus, AMBA bus protocols, Xilinx Vivado, Low power design techniques, systemverilog, SoC integration, Rtl Design, Static RTL checks, Lattice Diamond, STA timing closure, Axi