Timing Closure, Digital logic design using FPGAs, Debugging and problem-solving skills, FPGA Design Flow, Verilog RTL design, Timing Analysis

Embedded C, Verilog, Iar, Modelsim, Altera Signaltap, Jlink, Xilinx Ise, systemverilog, VHDL, Synopsys Identify, Xilinx Chipscope, Libero SoC, altera quartus, Jtrace

Qos, Ethernet, VLAN, Layer2, Axi, switching and routing concepts, DMA, LAYER3, Uvm, systemverilog

Usb, Perl, Verilog, Sata, Python, DV methodologies, PCI Express, Uvm, systemverilog, VMM, constrained random verification, functional coverage

Verilog, Unix Environment, Design verification experience, General Logic Design