Perl, Verilog, Python, Synthesis, processor design, low power design techniques, arithmetic units, Chisel, memory hierarchies, design for testing, timing power analysis, systemverilog, Asic Design Verification, accelerators, micro-architecture, bus architectures

Rtl Design, Verilog/SystemVerilog, Physical Design, Timing Analysis, FPGA Prototyping

Scripting Languages, Physical Design, floorplanning, EDA Tools