RTL integration, ASIC design flow, physical verification DRC LVS, power signal integrity signoff, Place And Route, floorplanning, advanced physical design methodologies and flows, hierarchical physical design strategies, RTL-to-GDSII implementation, Synthesis, power grid design, Timing Closure, AI ML-driven optimization in physical design tools, modern EDA tools and flows, Clock Tree Synthesis

Perl, automation, Python, Tcl, ASIC design flow, Synthesis, advanced physical design methodologies, RTL integration, scripting using Makefile, AI ML-driven optimization, Timing Closure, modern EDA tools, Verification, hierarchical physical design strategies, back-end physical design

redhawk , Perl, Pvs, Python Scripting, Tcl, Starrcxt, Calibre, QRC, Innovus, ICC2, primetime, Physical Design, Tempus, Voltus

synopsys primetime , Pvs, Perl, Python, Tcl, Mentor Calibre, Cadence Pegasus, PowerSI, ICC2, clock gating, Cadence Innovus, Synopsys Fusion Compiler, UPF, Synopsys IC Validator, Ansys RedHawk, CPF