Sta, PG creation and push-down methodologies, Physical Verification, SoC RTL to GDSII implementation, Scripting flow deployment, RDL knowledge, SoC Full-chip floorplanning, Die file generation, Feed-through planning, Hierarchical design implementation, PnR implementation

power integrity , Perl, Python, Tcl, Sta, primetime, Cadence Innovus, Tempus, EM IR analysis, Voltus

Automation Frameworks, Perl, Python, Tcl, AI-native automated methodologies, Methodology, Physical Design, Sub-3nm device physics

power integrity , Timing Closure, Process node design rules, Physical Design methodologies, Cadence toolchain, Signal Integrity

routing, floorplanning, Signal Integrity, CTS, Timing Closure, Placement, IR EM and variability analysis, low-power design, ASIC SOC physical design implementation, Physical Verification