About Marvell

Marvell's semiconductor solutions are the essential building blocks of the data infrastructure that connects our world. Across enterprise, cloud and AI, and carrier architectures, our innovative technology is enabling new possibilities.

At Marvell, you can affect the arc of individual lives, lift the trajectory of entire industries, and fuel the transformative potential of tomorrow. For those looking to make their mark on purposeful and enduring innovation, above and beyond fleeting trends, Marvell is a place to thrive, learn, and lead.

Your Team, Your Impact

Marvell Data Centre Engineering (DCE) - Compute & Storage (CCS) BU has been at the forefront of developing and delivering leading-edge, high performance data processing silicon platforms. By delivering a stream of technical innovations through a diverse set of fast‐growing product lines, Marvell Technology is powering the next‐generation data processing and workload acceleration platforms for the Carrier, Cloud/Enterprise and Automotive Compute market segments. The team focusses on the Custom ASIC business, Cloud AI solutions & Enterprise/Career solutions including the CXL product line

What You Can Expect

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Provide technical mentorship and people leadership, coaching junior engineers and helping grow overall team capability
Lead the definition of memory subsystem architecture, micro‑architecture, and register specifications for highly complex SoCs
Drive and review specifications, ensuring alignment across architecture, design, verification, and software teams
Lead architectural, performance, and design reviews with cross‑functional stakeholders, IP vendors, and customers
Guide and review RTL implementation, ensuring adherence to coding standards, design quality, and architectural intent
Work closely with third‑party IP vendors to define customization and integration requirements for controllers, PHYs, and related IP
Partner with physical design teams by reviewing and providing guidance on floorplanning, power analysis, synthesis, and timing signoff
Collaborate with verification teams on pre‑silicon activities, including test‑plan reviews, coverage analysis, full‑chip simulation/emulation, performance analysis, and debug
Drive continuous improvement of design and verification methodologies, tools, and execution models
Support and guide post‑silicon validation and software teams during prototype bring‑up, debug, and performance tuning
Own resource planning, task prioritization, execution tracking, and delivery commitments for the team

What We're Looking For

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Master's or Bachelor's degree in Computer Science, Electrical Engineering, or a related field with 18+ years of relevant industry experience, including technical leadership and people management
Proven experience in leading architecture, micro‑architecture, and register specification development for complex SoCs
Strong background in Verilog/SystemVerilog RTL design, including use of SystemVerilog assertions, with the ability to guide teams on best coding practices
Deep understanding of all stages of the ASIC development lifecycle, including specification, architecture, RTL implementation, integration, and prototype bring‑up
Strong expertise in high‑speed memory subsystems and protocols such as DDR4/5, LPDDR4/5X, and HBM3
Experience owning and delivering complex chips or large subsystems, such as network processors, CPUs, GPUs, NoCs, switches, or machine learning SoCs
Demonstrated success managing and reviewing full‑chip, subsystem, and block‑level architecture and design & Design Verification.
Domain expertise in one or more of the following is a strong plus: networking, embedded systems architecture, computer architecture, or machine learning accelerators
Proficiency in scripting languages such as Perl, Python, or Shell to support automation and flow improvements
Strong communication skills with experience interfacing with cross‑functional teams, IP vendors, and external customers

Additional Compensation and Benefit Elements

With competitive compensation and great benefits, you will enjoy our workstyle within an environment of shared collaboration, transparency, and inclusivity. We're dedicated to giving our people the tools and resources they need to succeed in doing work that matters, and to grow and develop with us. For additional information on what it's like to work at Marvell, visit our page.

All qualified applicants will receive consideration for employment without regard to race, color, religion, sex, national origin, sexual orientation, gender identity, disability or protected veteran status.

Interview Integrity

To support fair and authentic hiring practices, candidates are not permitted to use AI tools (such as transcription apps, real-time answer generators like ChatGPT or Copilot, or automated note-taking bots) during interviews.

These tools must not be used to record, assist with, or enhance responses in any way. Our interviews are designed to evaluate your individual experience, thought process, and communication skills in real time. Use of AI tools without prior instruction from the interviewer will result in disqualification from the hiring process.

This position may require access to technology and/or software subject to U.S. export control laws and regulations, including the Export Administration Regulations (EAR). As such, applicants must be eligible to access export-controlled information as defined under applicable law. Marvell may be required to obtain export licensing approval from the U.S. Department of Commerce and/or the U.S. Department of State. Except for U.S. citizens, lawful permanent residents, or protected individuals as defined by 8 U.S.C. 1324b(a)(3), all applicants may be subject to an export license review process prior to employment.

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Sr Staff Manager DDR/HBM