Python, Tcl, Calibre DRC, Skill, AI-assisted methodologies, Cadence Virtuoso, Analog layout fundamentals

DRC, LVS, semiconductor fundamentals, Parasitic Extraction, Cadence Virtuoso, ERC, precision analog layouts, analog layout design, CMOS technology

layout techniques for analog and mixed-signal circuits, Cadence Virtuoso Layout Editor VLE VXL, Mentor Graphics Calibre DRC LVS

Mentor Graphic Caliber, Cadence VLE, LVS, DRC, Antenna quality check

Mentor Graphic Calibre DRC, Cadence VLE, TSMC 3nm, Design and development of critical analog mixed-signal custom digital block, LVS, Full chip level integration support