RTL design in Verilog, Logic analyzers, Memory controller initialization code, systemverilog, Calibration algorithms

simvision , C, C++, Ovm, Front End Web Development, PERL, UI, Verilog, Python, Tcl, VMANAGER, SystemVerilog Assertions, Verdi, Uvm, Synopsys VCS, Incisive Xcelium, VMM, Coverage management, Modelsim

Tcl, C, Python, Perl, Shell, Uvm, systemverilog

System Verilog, X86, CPU Core Verification, Coverage models, Constrained-random tests, Scoreboards, Checkers, Uvm, Testbenches, RISC-V, ARM ISA, ISA behavior

SoC Verification, Uvm, Debugging Expertise, Verification Planning, C DPI Development, Scripting and Automation, systemverilog, Coverage-Driven Verification