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Showing 4 jobs
Skills:
Hdl Languages, Perl, Verilog, Python, Tcl, FPGA tools, quartus, VHDL, Vivado, systemverilog
Skills:
AMS verification, Verilog simulations, AI based automation, Sram, UVM Test Bench, DRAM, SystemVerilog PLI coding
Skills:
C, Vcs, Jtag, Perl, Verilog, Python, Tcl, UPF support, systemverilog, Scan Boundary Scan, VHDL, DFX Design Planning, Low Power technologies
Skills:
Perl, Shell scripting, Python, Tcl, power-aware simulation and verification, UPF Unified Power Format, power analysis tools and methodologies, static timing synthesis and implementation flows, low-power design methodologies, RTL design Verilog SystemVerilog, digital IC SoC design flow, CPF Common Power Format, EDA tools Synopsys Cadence Siemens Mentor
