Automation Frameworks, AMS verification, SV testbenches, UVM Test Bench, SystemVerilog PLI coding, DRAM Design Verification, Verilog simulations, Verilog Real Number Models, Digital Mixed Signal Verification, SV UVM based Verification

code coverage , Usb, Hdl Languages, DDR, Shell, Pcie, Perl, Debugging, Ethernet, Python, verification test plans, architectural design specifications, constrained-random test cases, verification requirements, UCIe, Uvm, systemverilog, CXL, simulation test benches

System Verilog, hardware verification concepts