Logic Design, Unit Testing, Backend, Synthesis, high speed design, LINT, ASIC design flow, Equivalence Check, cdc, Verification, Sta, ASIC synthesis constraints, Timing, Digital design concepts, Power estimation tools, IP level verification, Functional safety design, Front end implementation tools, Gate level simulations

static timing analysis, Shell, Perl, Verilog, Python, Tcl, EDA tools for synthesis, cdc, digital design principles, verification methodologies, Simulation, Timing Analysis, Rtl Design, spyglass, RDC, VHDL, ASIC development flow, RTL QC tools

Shell, Perl, Python, Tcl, Dft, BSEE, MSEE

Perl, Python, Tcl, constraint generation, Clock Tree Implementation Techniques, UPF, Rtl Design, Synthesis, STA using Primetime, Physical Verification, Verilog Coding, Timing Closure, ASIC Design, Power Estimation, Low Power Power Analysis, CPF, Validation, formal verification, Place and Route Implementation