Jtag, Verilog, System Verilog, C, C++, Perl, Python, Makefile

Pcie, System Verilog, Protocol analyzers, Verification and validation flows, Oscilloscopes, Uvm, Bring up tools

Ovm, Pcie, Verilog, Ethernet, System Verilog, power management flows, Uvm, HSIO, Low Power Verification, RTL GLS level simulations, SOC bot flow, System Verilog Assertions

Debugging, System Verilog, Axi, Problem-solving skills, CHI, ARM bus protocols, APB, SoC system architecture, Uvm, AHB, Virtual Memory concepts

Verilog, System Design, Automation

Tcl, System Verilog, Python, Perl, RTL Coding, Uvm, Simulation