Water heater storage and sizing based on ASHRAE Code, Rainwater system design and pipe sizing calculations, Technical software such as Hevacomp, Foul Drainage Flow Pipe sizing, Grease Oil and Lint interceptor design, Heat tracing design for Exposed cold and hot water distribution, Domestic cold Hot Water Demand and its pipe sizing, Secondary hot water looping design, Design selections for hot water heating systems, Basement open channel drain sizing

Verilog, Microprocessors, Usb, Logic Design, Pcie, LINT, cdc, pad ring, SoC clocking, Design Compiler, Synthesis, Asynchronous interface, SDCC, RTL Coding, Low power SoC design, micro-architecture, System-Verilog, SOC design, constraint development, chip level floorplan, Memory controller designs, reset debug architecture, AMBA protocols, primetime, Axi, APB, timing concepts for ASIC, Timing Closure, Multi Clock designs, AHB

perl, Shell, Scripting Languages, Tcl, Sta, Timing Analysis, Vlsi Design, Make flow, Timing Closure, constraints development, equivalence checks, low-power synthesis

Verilog, Logic Design, Physical Design, Timing Constraints, RTL constraints, LINT, Vlsi, timing exceptions, System-Verilog, cdc

CDC RDC Lint experience, RTL Verilog proficiency, AMD flows, SoC integration experience, Digital Design, Repeaters Register slice insertion, IO integration experience, Manual ECOs implementation, AMD xml-based flow, Subsystem integration experience

Verification methodology., IP design verification, Functional coverage, systemverilog, LINT, ARM SoCs, Rtl Design

Uart, Spi, Verilog, I2c, LINT, cdc, MAS development, Sub-system design, SoC integration, ip design, Quality check flows, AMBA bus protocols, Axi, APB, RTL Coding, Medium complexity protocol, AHB, Microarchitecture