Logic Design, Verilog, Microprocessors, low power design, LINT, cdc, Design Compiler, Memory controller designs, AMBA protocols, ASIC RTL Design, primetime, Synthesis, Axi, Asynchronous interface, APB, timing concepts for ASIC, RTL Coding, micro-architecture, Multi Clock designs, AHB, System-Verilog

Verilog, System Verilog, Sta, CDC tests, CPU ARM, RISC-V, backend tools, timing constraint files, low power design, Synthesis, Dft, VHDL, Pd, RTL Coding, Lint checks

Perl, Shell scripting, Python, Sta, SDC constraints, RTL design using Verilog, ASIC SoC development, Timing Analysis, systemverilog, digital design concepts, VHDL, Functional Verification, RTL debugging, UVM-based verification environments, Timing Closure, synthesis flows

FPGA Design, Perl, Verilog, Python, systemverilog, Synthesis Checks, Digital Design, Custom IP Development

C, Vcs, Perl, Verilog, Python, cdc, ASIC SoC development cycle, systemverilog, Rtl Design, spyglass, ASIC Design, formal verification

Clp, Pcie, Qc Tools, IPXACT, cdc, Vlsi, LINT, FIFO, UPF, AMBA, arbitration techniques, SDC, RDC, RTL Coding, VCLP

VLSI FIFO arbitration techniques, static QCs viz LINT CDC RDC CLP VCLP, design and integration for various in-house vendor IPs subsystems and SoC, RTL Coding, QC tools flows and IPXACT, constraints like SDC UPF

rtl development , static timing analysis, Verilog, Digital Signal Processing, LINT, Synthesis, Debug, LEC, Simulation, Matlab modeling, FPGA prototyping