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Showing 2 jobs
Skills:
static timing analysis, Logic Synthesis, Cadence-based ASIC design environments, micro-architecture development, SystemVerilog RTL design, Lint CDC formal verification, low-power design methodologies and flows
Skills:
static timing analysis, SystemVerilog RTL design, low-power design methodologies, micro-architecture development, LINT, Cadence-based ASIC design environments, formal verification, Dft, cdc, Logic Synthesis
