Ant, Latch-up, 7nm and below CMOS process geometries, Reliability, high speed GHz circuit design, LVS, process non-idealities, floorplanning, layout design for mixed analog digital ICs, Mentor Calibre, EMIR, Esd, signal flow planning, Cadence Virtuoso, ERC, DRC, isolation techniques, high performance data converters, signal and clock shielding

Ant, Latch-up, Reliability, Analog Layout Design, LVS, High Speed GHz Circuit Design, High Performance Data Converters, Signal Flow Planning, floorplanning, Mentor Calibre, CMOS Circuit Theory, Mixed Analog Digital ICs, EMIR, Isolation Techniques, Esd, Cadence Virtuoso, ERC, DRC, Clock Shielding