Verilog, System Verilog, Jasper, Simulation Tools, Synopsys VCS, Synopsys VC-Formal Magellan, Uvm, Cadence IES, Cadence IEV, Formal property checking tools

Jasper, Verilog, System Verilog, Synopsys VCS, Synopsys VC-Formal Magellan, Uvm, Cadence IES, Simulation Tools, Cadence IEV, Formal property checking tools

C, Systemc, Windows, Linux, Verilog, Makefile, Shell, Ruby, System Verilog, Perl, acceleration HLS tools process, graphics pipeline knowledge, debugging firmware and RTL code using simulation tools, automating workflows in a distributed compute environment, UVM testbenches, developing UVM based verification frameworks, TLM, simulation profile efficiency improvement, IP-level ASIC verification