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Showing 2 jobs
Skills:
System Verilog, Post-silicon validation, Test Architecture Methodology and Infrastructure, Test Static Timing Analysis, DFT CAD development, Logic Equivalency checking, JTAG protocols, ATPG, Scan and BIST architectures
Skills:
Vcs, System Verilog, primetime, JTAG protocols, Tessent, Logic Equivalency checking, ATPG, EDA Tools, TestMax, TetraMax, Scan and BIST architectures
