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Principal Engineer – Memory Training Architecture

AMD Ventures
Hyderabad, India

Skills:

C, Verilog, Perforce, Git, memory training algorithms, DDR5, systemverilog, Rtl Design, Sta, logic analyzers, compliance packages, AHB, ICManage, calibration algorithms, LPDDR6, LPDDR5, circuit timing, Embedded Systems, Axi

Early Applicant

Principal Engineer – Memory Training Architecture

Xilinx
X
Hyderabad, India

Skills:

C, Version Control Systems, Verilog, Perforce, Git, compliance packages, Pcb Design, silicon packaging, DDR5, systemverilog, Rtl Design, memory training architecture, logic analyzers, AHB, calibration algorithms, ICManage, LPDDR6, high speed scope, LPDDR5, circuit timing STA, Axi

Early Applicant
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