Perl, Verilog, Python, Tcl, VHDL, Uvm, systemverilog

Uart, python, Debugging, SV, test cases coding, Uvm, Test bench development, IJTAG, APB, Code and Functional coverage analysis, Axi, BUS Protocols

Nvme, Usb, Shell, Tcl, Verilog, System Verilog, Ethernet, Python, Pcie, Perl, DDR, UPF Low Power Verification, System Verilog Assertions, Uvm, Linux development environments, CHI, formal verification, CXL, Axi, NLP Testbench Verification, ASIC design flows

arm architecture , C, Usb, DDR, Pcie, Ethernet, SoC DV execution, hardware emulation support, TLMs in SystemC, Uvm, assertion-based formal verification tools, HBM

rtl verification , Verilog simulations, Sram, AI-assisted tools, Timing Analysis, DRAM, UVM Test Bench, SystemVerilog PLI coding

arm architecture , Usb, C, DDR, Pcie, Ethernet, hardware emulation support, SoC DV execution, TLMs in SystemC, Uvm, assertion-based formal verification tools, HBM

C, Requirements Traceability, Test Plan Creation, Tcl, Verilog, System Verilog, Python, Perl, Microprocessor architecture, interconnect, Assertions, UVM methodology, Gate Level Simulation, Testcase creation, Directed and constrained random methodologies, Metric Driven Verification, Coverage closure, Formal verification methodologies, SoC Verification, Functional and code coverage