static timing analysis, Python, Tcl, primetime, Tempus, high-speed design timing convergence, constraints synthesis, Clock Tree Synthesis, ECO flows

Soc, Bash, Perl, Python, Tcl, Siemens Calibre, Cadence Pegasus, Tempus, Cadence Innovus, Cadence Voltus, Cadence Genus, ASIC, Ansys RedHawk, Physical Design, GDSII

Routing, DDR design knowledge, floorplanning, Calibre, primetime, Innovus, RTL-to-GDSII implementation, Placement, EDA Tools, Genus, Tcl tool scripting, Physical Design Methodologies, MultiTap-CTS

Block level and Top-level physical implementation, Place and Route processes, Physical Design, Synthesis for high-speed designs

synopsys primetime , Routing, Perl, Python, Tcl, CTS, PTPX, Cadence Tempus, SDC, Synthesis, Eco, MMMC, Physical Design, STA Timing Closure, Digital Design

clocking , power integrity , LV EM IR Analysis, ESD Analysis, Physical Design Integration, RTL2GDS Implementation, Signal Integrity, PPA Power DRC Signoff, LVS clean-up, DRC, PNR Floor Plan, Power Mesh, Timing Signoff

redhawk , Synopsys ICC2, PNR and signoff tools, Cadence Innovus, Physical Verification, IR EM mitigation, PDN methodology, floorplanning, STA constraints, physical design implementation, primetime, Tempus, Voltus

DRC LVS clean signoff, Functional and physical ECOs, Placement and optimization, Physical design implementation, floorplanning, Setup hold timing closure, Timing convergence, Power grid design, Routing and post-route optimization