Perl, Python, Tcl, Synthesis, cdc, CHI, Ace, Verilog RTL development, AMBA protocols, systemverilog, RDC, LINT, Resets, performance optimization, debugging functional and performance issues

Logic Design, Rtl Design, Debug skills, Synthesis, Front-end design tools and methodologies, Micro-architecture, Static-timing closure, Custom SoC ASIC products, Gate-level simulations, Block-level function verification, formal verification

Dsp, Perl, Verilog, Front End Design, Tcl, Isp, RTL, Digital Design, Axia, Rtl Design, formal verification, VHDL, Timing Closure, HB