Physical Design Verification, Analog Circuit Design, Foundry PDKs, Embedded Design, Layout Design for Analog and Mixed-Signal Blocks

shielding , matching , Dac, Routing, EMIR verification, ADC, PEX, floorplanning, Cadence Virtuoso Layout XL, LVS, Pll, Analog Mixed-Signal Layout Design, advanced technology nodes, SERDES, ERC, Placement, DRC, Op-Amp, LDO, Bandgap, GXL

Vdc, ADC, Charge pump, density, Antenna, noise fixes, Vlsi Design, custom analog layout design, Virtuoso XL, EDA Tools, RV high voltage flows, LDO, scripting skills, layout validation, Circuit Design, DRCs

shielding , Layout verification tools, Analog Custom Layout Design, Advanced process nodes foundry rules, Common centroid, TI Texas Instruments project environment, DRC LVS ERC EM IR checks, Cadence Virtuoso, ESD latch-up prevention, Matching symmetry, Guard rings

Analog layout design, Mentor tools, Version-controlled design environment

Analog layout design, Design verification tools, Signal planning, IR ESD, Voltage drop, Process design rules, Micro-floor planning, TSMC N3 technology, Electron migration, High speed SerDes layouts