Calibre, Analog Layout, Cadence Virtuoso XL, Design for Manufacturability Principles, Signal Integrity Analysis, Power Distribution Techniques

DDR Timing, SDRAM functionality, ASIC design flow, ESD concepts, ODT, analog mixed signal design methodologies, JEDEC DDR interface requirements, layout methodologies, CMOS Circuit Design

Analog layout design, Design verification tools, Signal planning, IR ESD, Process design rules, Voltage drop, Micro-floor planning, TSMC N3 technology, Electron migration, High speed SerDes layouts

CMOS/FinFET Process Technology (28nm and below), Analog Mixed-Signal Layout, DRC/LVS/LPE Verification, Deep Submicron Effects Mitigation, ESD and Latch-Up Design, EM/IR and Power Routing Considerations

DC-DC Design, Power Electronics, Pcb Layout, Circuit Simulation, Analog Design, Validation

rc extraction , Automation, Programming Skills, Full-custom circuit layout verification, Circuit Design, Dfm, LVS, Cadence Virtuoso, Analog Layout, DRC, Mixed signal analog high speed layout, EMIR analysis

bandgap references , Comparators, Statistics, MOS Diodes, Transistor layout fabrication process, Analog Circuit Design, Monte Carlo analysis, Level Shifter, Schmitt Trigger, Statistical Distributions, Schematic generation, LDMOS, ESD protection circuits for CMOS IC, Power FETs, Amplifiers, Current Mirrors