hardware engineering , System Verilog, Test Planning, testbench stimulus agent monitor checker development, coverage driven constraint random verification, Uvm, c based reference model, unit and IP level verification

Perl, Verilog, Python, Tcl, Pre-Silicon test planning, low power concepts, RTL design for DFT, MBIST, DFT methodologies, systemverilog, Siemens Mentor Tessent, DFT Compiler, ATPG, Synopsys TetraMAX, DFT Integration Verification, Scan, Memory Repair, IJTAG

Perl, Python, Tcl, Synthesis, cdc, CHI, Ace, Verilog RTL development, AMBA protocols, systemverilog, RDC, LINT, Resets, performance optimization, debugging functional and performance issues

MATLAB, Transistor Level Design, Verilog A modeling, RF High-Speed broadband techniques, Simulink, Ultra-low-power analog circuits, High-speed data converter architectures, Digitally assisted analog circuits

Verilog, Scripting Languages, Synthesis, collaborating with analog teams on mixed-signal data paths, functional safety mechanisms, RTL-to-GDSII design flows, safety architectures for MCUs SoCs and automotive ECUs, systemverilog, Dft, silicon bring-up and debug, Embedded Systems, Timing Closure, automotive software development, microcontroller and Flash Controller architectures, lint and CDC analysis, Hardware Design