System Verilog, Post-silicon validation, Test Architecture Methodology and Infrastructure, Test Static Timing Analysis, DFT CAD development, Logic Equivalency checking, JTAG protocols, ATPG, Scan and BIST architectures

Tcp, Pcie, Perl, Ethernet, Python, System Verilog, Forwarding logic Parsers P4, RDMA, Building test benches from scratch, Palladium, Zebu, Veloce, ASIC verification using UVM, HAPS, formal verification