Shell, Perl, Python, Verilog-AMS, Wreal, Cadence Virtuoso AMS Designer, Uvm, systemverilog, Verilog-A

Verilog, random stimulus, assertion-based verification, Uvm, bus functional models, functional coverage, scoreboards, checkers, advanced verification methodologies, VMM, systemverilog, monitors

Python, Digital Flows, EDA Tools, RTL, DV Automation, CI/CD