Network Security, DDR, Pcie, Ethernet, Static Timing Analysis, Arm, LINT, gate-level simulations, RTL implementation, cdc, mixed-mode simulations, RISC-V, Cadence, UPF techniques, systemverilog, RDC, tools such as Synopsys, design closure, Verification, Mentor Graphics

Spi, DDR, Shell, Pcie, Debugging, I2c, Python, Scripting, Uart, Perl, Ethernet, Tcl, SoC emulation, Boot flow, High-speed protocols, HBM, ZeBu, emulation platforms, Memory interfaces, Palladium, system initialization, Security Architecture, Peripheral interfaces, Veloce, CXL, USB 3.0

C, Usb, Shell Scripting, Spi, Device Driver Development, Operating Systems, Gpio, I2c, Linux Kernel, Python, ADC, Wi-Fi, Embedded Systems

Verilog, VHDL, RTL Coding, debugging RTL logic

Git, Shell scripting, Python, WLAN standards IEEE 802.11

windows automation , Jenkins, PowerShell, Mariadb, MongoDB, Groovy, Python, C Sharp, BAT scripting

Scripting, Digital Logic Design, Lint checks, Clock domain crossing analysis, ECO flows, Static-timing-analysis, RTL Coding

Logic Design, Verilog, Sta, Synthesis, block and top-level timing constraints, Power product design, mixed signal integrated circuits, Scan Insertion, Timing Analysis, design constraints, ATPG generation, synthesis scripts, RTL Coding, micro-architecture, System-Verilog

Shell, Logic Design, Tcl, Python, Perl, Cadence, MBIST OCC validation flows, Synopsys, IEEE 1687 IJTAG standards, Scan insertion and ATPG tools, Digital Circuit Design, Hierarchical DFT and SDC constraint management, SpyGlass DFT rules, Mentor, Sta, SSN design, Physical design flows, Debug, RTL design synthesis