Perl, Python, Tcl, constraint generation, Clock Tree Implementation Techniques, UPF, Rtl Design, Synthesis, STA using Primetime, Physical Verification, Verilog Coding, Timing Closure, ASIC Design, Power Estimation, Low Power Power Analysis, CPF, Validation, formal verification, Place and Route Implementation

Perl, Verilog, Python, Tcl, CTS, Post-Route Optimization, Synthesis, VHDL, Placement, CDNS, SNPS, P and R tools

Perl, Awk, Automation, Python, Tcl, Power signoff, Physical Design Implementation, ECO generation, Timing Signoff, GDSII

Shell, Perl, Python, Tcl, Sta, timing optimization, netlist-to-GDSII, Physical Verification, global routing, PNR, full chip floorplan, power integrity analyses

Scripting, PERL, Tcl, Sta, CTS, Full-chip Floor-planning, Timing Convergence, RTL2GDSII flow, ICC2, Tempus, primetime, Innovus, Physical Verification, Synthesis, Layout Closure, Physical Design, Timing Closure, High Frequency Design Methodologies, Place And Route

power integrity , static timing analysis, Soc, Shell Scripts, Perl, automation, Scripting, Python, Tcl, Implementation, timing ECO, Physical Design, Physical Verification, ASIC, EDA Tools, IR EM analysis, CMOS tech nodes