About Marvell

Marvell's semiconductor solutions are the essential building blocks of the data infrastructure that connects our world. Across enterprise, cloud and AI, and carrier architectures, our innovative technology is enabling new possibilities.

At Marvell, you can affect the arc of individual lives, lift the trajectory of entire industries, and fuel the transformative potential of tomorrow. For those looking to make their mark on purposeful and enduring innovation, above and beyond fleeting trends, Marvell is a place to thrive, learn, and lead.

Your Team, Your Impact

The Custom Compute and Storage (CCS) Business Unit collaborates with strategic customers
to develop advanced SoCs-from architecture through production.
The Emulation Center of Excellence (CoE) plays a critical role in:
. Delivering scalable emulation infrastructure
. Enabling pre-silicon validation
. Driving software readiness and post-silicon success
In this role, you will lead and contribute to emulation of key subsystems including:
. Boot and Security
. High-speed interfaces: PCIe, CXL, Ethernet
. Memory subsystems: DDR, HBM
. Low-speed peripherals: SPI, I2C, UART
. USB 3.0

What You Can Expect

. Lead the development of complex SoC emulation models, including design

integration, environment setup, compilation, and debug across industry-leading platforms

(e.g., Veloce, ZeBu, Palladium).

. Drive emulation bring-up activities, including clock/reset sequencing, firmware boot,

and system validation using pre-silicon hardware models.

. Create and execute emulation test plans to support verification, performance

analysis, software development, and system validation needs across multiple teams.

. Collaborate closely with RTL design, verification, and firmware teams to define

requirements, develop accurate hardware models, and ensure seamless integration into

the emulation environment.

. Debug complex SoC and subsystem issues across RTL, firmware, emulation

platforms, and toolchain interactions.

. Optimize emulation performance, including model partitioning, timing, and runtime

efficiency.

. Automate flows and improve productivity through scripting (Python, Perl, Tcl, shell)

and tooling enhancements.

. Interface with EDA vendors (Synopsys, Cadence, Siemens) to evaluate tool

capabilities, resolve technical issues, and drive feature improvements.

. Define and execute emulation strategy for complex SoCs across multiple subsystems

(Boot, Security, PCIe, CXL, DDR, HBM, USB, Ethernet, and peripherals)

. Develop and drive subsystem-level and full-chip emulation test plans

. Enable pre-silicon validation of firmware, boot flows, and security features

. Collaborate with cross-functional teams to bring up and debug:o PCIe / CXL link and protocol issues

o DDR / HBM initialization and performance validation

o Ethernet and USB 3.0 integration

o Low-speed peripheral functionality (SPI, I2C, UART)

. Enable firmware and software teams by providing stable and scalable emulation

environments

What We're Looking For

.Bachelor's degree with 18+ years, or Master's/PhD with 15+ years in Electrical

Engineering, Computer Science, or related field

.Strong experience in SoC emulation, validation, and debug

.Expertise in one or more domains:

oBoot flow and system initialization

oSecurity architecture and validation

oHigh-speed protocols: PCIe, CXL, Ethernet

oMemory interfaces: DDR, HBM

oPeripheral interfaces: SPI, I2C, UART, USB 3.0

.Deep understanding of SoC architecture, interconnects, and system-level integration

.Hands-on experience with emulation platforms (Palladium, ZeBu, Veloce)

.Strong debugging skills across HW/SW boundary

.Proficiency in scripting: Python, Perl, Tcl, Shell

.Proven ability to lead cross-functional efforts and drive execution

Additional Compensation and Benefit Elements

With competitive compensation and great benefits, you will enjoy our workstyle within an environment of shared collaboration, transparency, and inclusivity. We're dedicated to giving our people the tools and resources they need to succeed in doing work that matters, and to grow and develop with us. For additional information on what it's like to work at Marvell, visit our page.

All qualified applicants will receive consideration for employment without regard to race, color, religion, sex, national origin, sexual orientation, gender identity, disability or protected veteran status.

Interview Integrity

To support fair and authentic hiring practices, candidates are not permitted to use AI tools (such as transcription apps, real-time answer generators like ChatGPT or Copilot, or automated note-taking bots) during interviews.

These tools must not be used to record, assist with, or enhance responses in any way. Our interviews are designed to evaluate your individual experience, thought process, and communication skills in real time. Use of AI tools without prior instruction from the interviewer will result in disqualification from the hiring process.

This position may require access to technology and/or software subject to U.S. export control laws and regulations, including the Export Administration Regulations (EAR). As such, applicants must be eligible to access export-controlled information as defined under applicable law. Marvell may be required to obtain export licensing approval from the U.S. Department of Commerce and/or the U.S. Department of State. Except for U.S. citizens, lawful permanent residents, or protected individuals as defined by 8 U.S.C. 1324b(a)(3), all applicants may be subject to an export license review process prior to employment.

#LI-RV1

Senior Principal Engineer, Subsystem CoE Emulation