Hard IP integration, Clock and Power distribution, STA setup convergence methodology, Power Integrity Analysis, Hierarchical design implementation, Automation scripts within STA tools, Timing Closure, Timing ECO Implementation, Floor Planning, Debugging skills in implementation issues, ASIC Physical implementation, Global signal planning, Physical convergence, Tweaker Primetime based ECO flows

Python/Perl programming., Rtl Design, FPGA/silicon bring-up, ASIC methodology, ARM-based SoCs, Microarchitecture, systemverilog

ASIC IP Design, SystemVerilog Assertions, systemverilog

Fcoe, Ethernet, spyglass, Verilog RTL coding, Verplex LEC, high-speed serial interfaces, Synopsys Design Compiler, multi-domain clock synchronization, high performance memory subsystems, ASIC debugging

Verilog, IEEE 1500, VHDL, IEEE 1149.1, EDA tools for ASIC design verification and testing, Low-power design techniques

Cache, Verilog, LINT, Synthesis, cdc, memory compression, timing power analysis, digital logic design principles, systemverilog, logic synthesis techniques, Dft, RTL design concepts, RDC, fabric coherence, ASIC design methodologies, DRAM, low-power design techniques

rtl development , power delivery , Verilog, ASIC design flow, Dft, mixed-signal chips, Behavioral Circuit Modeling, Timing Analysis, Custom Digital Design, power management solutions, System-Verilog