Physical Design, MBIST, Synopsys, Synthesis, ATPG, LBIST, cdc, Dft, Rtl Design, Cadence

boundary scan , Jtag, Perl, Scripting Languages, Python, scan compression, Scan Insertion, memory BIST, DFT methodologies, test pattern generation, DFT tools, Cadence Modus, ATPG, Genus

Perl, Verilog, Python, Tcl, Cadence Tools, Modus DFT, Xcelium Simulation, Scan Insertion, MBIST, Genus Synthesis, DFT sign-off, VHDL, DFT architecture, ATPG, Fault Simulation

Python Scripting, Jtag SoC debugging, Basic PrimeTime, SystemVerilog UVM, Strong TCL scripting capability

physical design flows, Scan Insertion, compression techniques, MBIST, Cadence, Mentor, STA synthesis, DFT tools, DFT architecture implementation, ATPG, LBIST, Synopsys

Jtag, Desing, MBIST