Unit Testing, Performance, Verilog, Synthesis, cdc, post-silicon validation, design documentation, code reviews, power-related issues, systemverilog, LINT, silicon bring-up, Power, block-level design integration, design optimization

Vcs, DDR, Verilog, Digital Signal Processing, Synthesis, RTL simulation, neural network accelerators, STA tools, floating-point computation, Sram, systemverilog, Rtl Design, Axi, motion control systems, linting, Modelsim, AHB

Logic Design, Rtl Design, Debug skills, Synthesis, Front-end design tools and methodologies, Micro-architecture, Static-timing closure, Custom SoC ASIC products, Gate-level simulations, Block-level function verification, formal verification

FPGA-SoC interfacing, Python Perl, Peripheral interfaces SPI I2C UART DDR4, Xilinx FPGA design and prototyping, AMBA protocols AXI AHB APB, Protocol analyzers SPI CAN Ethernet, Hardware debugging tools Oscilloscope Logic Analyzer, Micro-architecture definition and logic design, Implementation of DSP algorithms on FPGA Radar EW systems, RTL Design using Verilog VHDL, Constraints development linting CDC analysis, Simulation and verification methodologies, FPGA synthesis implementation and timing closure, High-speed interfaces PCIe Ethernet JESD204B C

Logic Design, Gate-level simulations, formal verification, Synthesis, Static-timing closure, Custom SoC ASIC products, Debug skills, Block-level function verification, Front-end design tools and methodologies, Micro-architecture, Rtl Design

rtl development , Fpga, LINT, cdc, ASIC, RTL Netlist, RTL Coding, hardware design tools, front end design flow

Computer Architecture, reset methodologies, Timing Constraints, Microarchitecture, digital RTL design