Perl, Python, constraint-random tests, Power-aware verification, formal static verification techniques, coverage-driven verification methodologies, Uvm, systemverilog

Logic Design, Rtl Design, Debug skills, Synthesis, Front-end design tools and methodologies, Micro-architecture, Static-timing closure, Custom SoC ASIC products, Gate-level simulations, Block-level function verification, formal verification

C, Usb, Shell Scripting, Spi, Device Driver Development, Operating Systems, Gpio, I2c, Linux Kernel, Python, ADC, Wi-Fi, Embedded Systems

Agile Development Methodologies, Embedded Systems Development, Python Programming, Software development verification and system failure analysis, Software development best practices, SSD firmware simulation development, Operating systems and system level concepts, NAND flash memory design and internals

Perl, Verilog, Python, Tcl, Pre-Silicon test planning, low power concepts, RTL design for DFT, MBIST, DFT methodologies, systemverilog, Siemens Mentor Tessent, DFT Compiler, ATPG, Synopsys TetraMAX, DFT Integration Verification, Scan, Memory Repair, IJTAG

Debugging, mixed signal CMOS IC design, Analog Design, silicon testing, ADC design

Scripting languages (Perl), Industry-standard simulators (VCS, Verilog, IP core verification, UVM/VMM/OVM methodologies, Functional and code coverage