Register modeling, Regression management, SERDES, coverage analysis, Uvm, Firmware interaction, systemverilog, PHY architectures

Python, Uvm, systemverilog, Coverage Closure, Gate Simulation, Asic verification

Fpga, Logic Design, Verilog, Sta, Synthesis, Power product design, TCL scripts, Scan Insertion, Timing Analysis, design constraints, Uvm, ATPG generation, regression frameworks, formal verification, Timing Constraints, synthesis scripts, ABV, RTL Coding, micro-architecture, Functional Verification, System-Verilog, Digital Verification

hardware engineering , Test Planning, System Verilog, testbench stimulus agent monitor checker development, coverage driven constraint random verification, Uvm, c based reference model, unit and IP level verification