Fpga, Logic Design, Verilog, Uvm, Timing Constraints, TCL scripts, regression frameworks, Timing Analysis, Power product design, System-Verilog, RTL Coding, Functional Verification, Sta, micro-architecture, ATPG generation, formal verification, synthesis scripts, Synthesis, ABV, design constraints, Digital Verification, Scan Insertion

Unix, Shell, C, Perl, Linux, Verilog, Python, Uvm, systemverilog

C, Python, Uvm, systemverilog

Scala, Python, System Verilog, Chisel, Uvm

DVCS e.g. Git, Gcc, Sql, Xslt, Basic Of Python, System Verilog, Javascript, Uvm, SGE or other DRMS, Web programming – HTML DOM, Verification experience in the relevant industry, Assembly languages, SVA, XML and XPath, LLVM

Debugging, Mixed-Signal Verification, Uvm, systemverilog

Scalability, Python, Git, Agile Methodologies, Oop, UFS, Reliability, Performance optimization, Flash Memory concepts, eMMC, Observability tools