Embedded C, Verilog, Iar, Modelsim, Altera Signaltap, Jlink, Xilinx Ise, systemverilog, VHDL, Synopsys Identify, Xilinx Chipscope, Libero SoC, altera quartus, Jtrace

arm architecture , C, Usb, DDR, Pcie, Ethernet, SoC DV execution, hardware emulation support, TLMs in SystemC, Uvm, assertion-based formal verification tools, HBM

arm architecture , Axi, verification methodologies, APB, verification tools for simulation and debug, Uvm, AHB

Clp, Perl, shell scripting, System Verilog, Python, Tcl, LINT, cdc, LEC, RDC, RTL static checks, VCLP

Assembly Language, C, Ovm, PERL, Verilog, Shell script, System Verilog, Systemc, System Verilog PLI, Uvm, Emulation, Functional Verification, DPI interface, SoC Verification

Usb, Ovm, Pcie, Ethernet, Test and coverage plan, Verification environment, Uvm, Assertion checkers, VMM Test Harness, MIPI, Coverage and scenario creation, Validation plan, System Verilog HVL

Dsp, Soc, C Shell, Gpu, Jtag, Perl, System Verilog, Python, Tcl, Ip, Ai, AMBA protocols, Uvm, Axi, APB, AHB