Shell, C, Perl, Python, Tcl, Uvm, systemverilog

assertion based verification , Debugging Tools, Scripting Languages, systemverilog, Uvm, Testbench Development, FPGA Prototyping, coverage analysis, Design Simulation, Design Verification, Asic verification, SoC Verification

Databases, Perforce, Vcs, HTML, Networks, Git, REST, Javascript, Perl, Web development, Linux Shell Scripting, Python, source control systems, Verdi, waveform debug tools, RTL design verification tools, Simulators, ASIC EDA tool flows, filers, LSF compute farms, Makeppfiles, Jenkins build servers

Debug Root Cause Analysis, Verification Planning, Uvm, SoC Verification, systemverilog, Functional Coverage, Assertion-based Verification

rtl verification , Verilog, Python, FineSim, AI tools, AMS verification, Hspice, Transistor-Level Verification, Spice, Uvm, systemverilog

Arm, C, verification methodologies, Uvm, RISCV, functional coverage, Verification Tools, DSP core

C, Makefile, Soc Architecture, Windows, Perl, Linux, Verilog, Python, System Verilog, Systemc, ASIC Design Flow, debugging skills in functional simulations, UVM testbenches, automating workflows in a distributed compute environment, Asic Design Verification