About Marvell

Marvell's semiconductor solutions are the essential building blocks of the data infrastructure that connects our world. Across enterprise, cloud and AI, and carrier architectures, our innovative technology is enabling new possibilities.

At Marvell, you can affect the arc of individual lives, lift the trajectory of entire industries, and fuel the transformative potential of tomorrow. For those looking to make their mark on purposeful and enduring innovation, above and beyond fleeting trends, Marvell is a place to thrive, learn, and lead.

Your Team, Your Impact

Work Across on the creation and optimization of customizable memory instances and compilers (SRAM, Register Files, etc.) for chips, defining architectures, driving PPA (Performance, Power, Area), mentoring teams, and ensuring integration, requiring deep expertise in custom analog/digital design, EDA tools (Cadence, Synopsys), and scripting for automation, often with experience in advanced nodes and foundry/vendor collaboration.

What You Can Expect

Own the design and implementation of at least one major sub-circuit block, from architecture definition to fine-tuning. Perform schematic entry using Cadence Virtuoso, conduct circuit simulations with Spectre, MDL, and post-layout tools, and verify designs using Verilog. Develop SRAM views, including timing characterization. Conduct statistical analysis (Monte Carlo) across Process, Voltage, and Temperature (PVT) variations. Identify and propose innovative solutions to enhance power-performance-area metrics. Collaborate with the physical design team to create optimal GDS layouts. Partner with the Hardware and Silicon Validation Team for silicon evaluation. Analyze, summarize, document, and present results effectively.

What We're Looking For

Bachelor's or Master's degree in Electrical Engineering, Computer Engineering, or a related field.
3+ years of hands-on experience in digital circuit design, with a focus on custom memory circuit design (sense amps, periphery), analog/digital CMOS, semiconductor physics, DFT, Verilog/VHDL, scripting (Perl/Python/TCL).
Tools:Cadence Virtuoso, Synopsys tools (Design Compiler, PrimeTime), HSPICE, Spectre, solido.
Experience:Deep sub-micron nodes (7nm/5nm/3nm), compiler IP development, foundry PDKs, memory characterization.

Additional Compensation and Benefit Elements

With competitive compensation and great benefits, you will enjoy our workstyle within an environment of shared collaboration, transparency, and inclusivity. We're dedicated to giving our people the tools and resources they need to succeed in doing work that matters, and to grow and develop with us. For additional information on what it's like to work at Marvell, visit our page.

All qualified applicants will receive consideration for employment without regard to race, color, religion, sex, national origin, sexual orientation, gender identity, disability or protected veteran status.

Interview Integrity

To support fair and authentic hiring practices, candidates are not permitted to use AI tools (such as transcription apps, real-time answer generators like ChatGPT or Copilot, or automated note-taking bots) during interviews.

These tools must not be used to record, assist with, or enhance responses in any way. Our interviews are designed to evaluate your individual experience, thought process, and communication skills in real time. Use of AI tools without prior instruction from the interviewer will result in disqualification from the hiring process.

This position may require access to technology and/or software subject to U.S. export control laws and regulations, including the Export Administration Regulations (EAR). As such, applicants must be eligible to access export-controlled information as defined under applicable law. Marvell may be required to obtain export licensing approval from the U.S. Department of Commerce and/or the U.S. Department of State. Except for U.S. citizens, lawful permanent residents, or protected individuals as defined by 8 U.S.C. 1324b(a)(3), all applicants may be subject to an export license review process prior to employment.

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Staff Engineer- SRAM Memory Compiler Development