Manager, Technology, Principal

DFT constraints, DFX, Analog Patterns flow, SPyglass flows, Mixed Signal chips

Nvme, Mac, Pcie, sfr, PHY, SoC integration, Speed negotiation, Enumeration, APST, Firmware design, ASIC, power management, Link training, Error handling, Link power management

LINT, Soft IP collateral, cdc, high accuracy analog systems, ARM Protection units, ARM CM4, RTL integration, ip development, ROM controllers, UPF, Axi, Timing Constraints, DMA controllers, SoC micro architecture, AHB