ASICs, formal verification, GLS low-power DV, LPDDR, Uvm, assertion-based verification, memory system architecture, systemverilog, standard IP components, performance verification

Tcp, Pcie, Ethernet, System Verilog, RDMA, Palladium, Test benches, Zebu, Veloce, ASIC verification using UVM, HAPS, Data path verification, formal verification

Tcp, Pcie, Ethernet, System Verilog, RDMA, Data path verification performance tests, Building test benches, Palladium, Zebu, Veloce, ASIC verification using UVM, HAPS, formal verification

System Verilog, Building test benches from scratch, ASIC verification using UVM

Perl, Python, Tcl, Emulation, systemverilog, System Verilog Assertions