Meet the Team

Define, design and verify ASIC and ASIC subsystems to be deployed in a range of Cisco platforms. Contribute to a multi-disciplined engineering team to meet the power, performance, and area goals for products. Design, document, and develop ASIC subsystems for release in high volume and quality. Help define the process, methods, and tools for design and implementation of complex developments.

Your Impact

Collaborate with Front-end and Back-end teams to understand chip architecture and guide them in refining design and timing constraints for seamless physical design closure. As part of this team, you will contribute to develop next generation networking chips.

You need to possess a deep understanding of timing constraints, including clock groups, exceptions, and clock exclusivity. Proficient in industry standard SDC/DTA tools and scripting for automation. Excel at identifying and resolving timing issues across all design levels.

Being a member of design team who oversees fullchip SDCs and works with physical design and DFT teams to close fullchip timing in multiple timing modes.
Option to also do block level RTL design or block or top-level IP integration.
Helping develop efficient methodology to promote block level SDCs to fullchip, and to bring fullchip SDC changes back to block level.
Helping develop and apply methodology to ensure correctness and quality of SDCs as early as possible in design cycle.
Reviewing block level SDCs and clocking diagrams and mentor other RTL design owners on SDC development.
Creating fullchip clocking diagrams and related documentation.

Minimum Qualifications

Bachelors + 8 years of related experience, or Masters + 6 years of related experience, or PhD + 1 year of related experience.
Experience with block / full chip SDC development in functional and test modes.
Experience in Static Timing Analysis and prior working experience with STA tools like PrimeTime/Tempus.
Understanding of related digital design concepts (e.g. clocking and async boundaries)
Experience with Synthesis tools (e.g. Synopsys DC/DCG/FC), Verilog/System Verilog programming.

Preferred Qualifications

Experience with constraint analyzer tools such as TCM (Timing Constraint Manager from Synopsys) and CCD (Conformal Constraint Designer from Cadence)
Experience with Spyglass CDC and Glitch analysis.
Experience using Formal Verification: Synopsys Formality and Cadence LEC.
Experience with scripting languages such as Python, Perl, or TCL.

Why Cisco

At Cisco, we're revolutionizing how data and infrastructure connect and protect organizations in the AI era – and beyond. We've been innovating fearlessly for 40 years to create solutions that power how humans and technology work together across the physical and digital worlds. These solutions provide customers with unparalleled security, visibility, and insights across the entire digital footprint.

Fueled by the depth and breadth of our technology, we experiment and create meaningful solutions. Add to that our worldwide network of doers and experts, and you'll see that the opportunities to grow and build are limitless. We work as a team, collaborating with empathy to make really big things happen on a global scale. Because our solutions are everywhere, our impact is everywhere.

We are Cisco, and our power starts with you.

ASIC Engineer || SDC || Design and Timing Constraints | Exp 8+ years