Verilog, System Verilog, Functional Verification, LPDDR, Uvm, DDR memory protocols, HBM

C, System Verilog, Python, Design implementation, Synthesis, Behavioral coding, Synthesis and SDC Creation, low power design, Debugging verification test cases, Digital architecture, Digital RTL, Scripting of design automation, Embedded uC Designs, Timing Analysis

Systemc, Test Planning, C, Shell, Tcl, Verilog, Python, systemverilog, NoC bus and interconnect verification, assertions, transaction-level modeling, UVM-based testbench development, constrained-random verification, formal verification, power-aware verification