About Marvell

Marvell's semiconductor solutions are the essential building blocks of the data infrastructure that connects our world. Across enterprise, cloud and AI, and carrier architectures, our innovative technology is enabling new possibilities.

At Marvell, you can affect the arc of individual lives, lift the trajectory of entire industries, and fuel the transformative potential of tomorrow. For those looking to make their mark on purposeful and enduring innovation, above and beyond fleeting trends, Marvell is a place to thrive, learn, and lead.

Your Team, Your Impact

Marvell Data Centre Engineering (DCE) - Compute & Storage (CCS) BU has been at the forefront of developing and delivering leading-edge, high performance data processing silicon platforms. By delivering a stream of technical innovations through a diverse set of fast‐growing product lines, Marvell Technology is powering the next‐generation data processing and workload acceleration platforms for the Carrier, Cloud/Enterprise and Automotive Compute market segments. The team focusses on the Custom ASIC business, Cloud AI solutions & Enterprise/Career solutions including the CXL product line

What You Can Expect

Own and drive PCIe/CXL subsystem micro architecture definition, RTL implementation, and integration
Collaborate closely with Architecture teams to translate requirements into robust RTL designs
Work with Design Verification teams on test‑plan reviews, debug, and coverage closure
Partner with Physical Design and DFT teams to ensure PD‑friendly and DFT‑ready RTL
Support silicon bring‑up and post‑silicon debug, working with firmware and validation teams
Drive design quality improvements, coding best practices, and reuse across projects
Participate in design reviews, milestone reviews, and cross‑functional technical discussions
Mentor junior designers and provide technical leadership within the PCIe/CXL design domain

What We're Looking For

Master's/Bachelor's degree in Electronics/Electrical Engineering with 18+ years of relevant experience in RTL design
Experience on end‑to‑end PCIe/CXL subsystem RTL design execution and sign‑off
Proven experience delivering complex PCIe/CXL IP or subsystems from architecture through RTL closure
Strong hands‑on experience in SystemVerilog / Verilog RTL development
Expertise in PCIe protocol architecture including link, transaction, and PHY interaction layers
Strong understanding of CXL.io, CXL.cache, and CXL.mem architectures
Deep knowledge of ARM‑based SoC integration and AMBA protocols (AXI‑4, CHI, ACE)
Experience designing high‑performance, low‑latency data paths and handling ordering, coherency, and error mechanisms
Solid grasp of Clocking, Resets, CDC/RDC, low‑power techniques, and performance optimization
Experience supporting lint, CDC/RDC, synthesis, and design sign‑off flows
Proficient in debugging functional and performance issues at subsystem and SoC levels
Experience using industry‑standard EDA tools from Synopsys, Cadence, Mentor/Siemens
Proficient in scripting languages such as Tcl / Perl / Python
Experience with version control systems such as GIT, SVN, etc.

Additional Compensation And Benefit Elements

With competitive compensation and great benefits, you will enjoy our workstyle within an environment of shared collaboration, transparency, and inclusivity. We're dedicated to giving our people the tools and resources they need to succeed in doing work that matters, and to grow and develop with us. For additional information on what it's like to work at Marvell, visit our Careers page.

All qualified applicants will receive consideration for employment without regard to race, color, religion, sex, national origin, sexual orientation, gender identity, disability or protected veteran status.

Interview Integrity

To support fair and authentic hiring practices, candidates are not permitted to use AI tools (such as transcription apps, real-time answer generators like ChatGPT or Copilot, or automated note-taking bots) during interviews.

These tools must not be used to record, assist with, or enhance responses in any way. Our interviews are designed to evaluate your individual experience, thought process, and communication skills in real time. Use of AI tools without prior instruction from the interviewer will result in disqualification from the hiring process.

This position may require access to technology and/or software subject to U.S. export control laws and regulations, including the Export Administration Regulations (EAR). As such, applicants must be eligible to access export-controlled information as defined under applicable law. Marvell may be required to obtain export licensing approval from the U.S. Department of Commerce and/or the U.S. Department of State. Except for U.S. citizens, lawful permanent residents, or protected individuals as defined by 8 U.S.C. 1324b(a)(3), all applicants may be subject to an export license review process prior to employment.

Principal Engineer - PCIe RTL Design