Mixed-signal circuit design, PPA tradeoffs, Memory Cell Design, PLL clock-generation, Layout collaboration, Charge Pumps, Transistor-level design simulation, Clock buffers, Analog Design, Loop Filters

bandgap references , IC level issues, IC development flow, ESD LU, Silicon debugs, High speed level shifters, Design extraction and simulation flows, Temperature Sensor, Switch Cap circuits, Analog feedback loops, Analog Circuit Design, Analog Buffers, Source-Sink LDOs, Ultra-low power Oscillators, Op-Amps, Simulation and Verification, Analog layouts, LDOs, Current Sense SAR ADCs, Charge Pumps, Control Loops, Control loop architectures, Comparators

Full product development cycle, Quality requirements for automotive products, power management, CMOS BCD Analog Circuits

bandgap references , temperature sensors , AC simulations, Schematic Maestro, frequency response, mixed-signal circuit design, low-noise Sigma-Delta converters, DC operating point, op-amps, mismatch analysis, biasing circuits, noise, INL, precision analog circuits, DNL, Stability, CMOS technologies, ADEXL, Layout XL, LDOs, THD, Spectre AMS, Cadence Virtuoso suite

C, Tcl, Python, Perl, PrimeSim, LVS, CMOS design, Spectre, ADE, high-speed analog design, Custom Compiler, post-layout extraction, Cadence Virtuoso, DRC, Hspice, Circuit Simulation

regulators , Verilog, Matlab, lab testing skills, IC design CAD tools, Bandgap bias circuits, TX, RX, Spice, ADCs, high-speed design techniques, Spectre, Pll, DACs, HSIM, Filters, deep sub-micron CMOS technologies

Verilog, Cadence IC design flow and tools, POR circuits, FPGA design generation flow, ADCs, Circuit theory design and layout, Lab testing of analog blocks, High accuracy comparators, DACs, VHDL, Filters, Mixed-signal circuits, Analog Design, Bandgap