C, Makefile, Windows, Shell, Perl, Linux, Verilog, Ruby, System Verilog, Systemc, IP level ASIC verification, graphics pipeline knowledge, acceleration HLS tools, Simulation Tools, RTL code, UVM testbenches, automating workflows, simulation profile efficiency improvement, UVM based verification frameworks, TLM, debugging firmware, testbenches processes and flows

Verilog, Unix Environment, General Logic Design, Design verification experience

Verilog, Unix Environment, General Logic Design concepts