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Job Description:

Job Summary

We are looking for a highly motivatedSenior Engineer I - Design with a strong understanding offull-chip SoC architectureto join our engineering team. This role requires hands-on expertise across bothRTL design and verification, with responsibility for delivering high-quality, fully verified designs from concept through tape-out. The ideal candidate combines deep technical knowledge with a system-level mindset, Latest AI know how and strong cross-functional collaboration skills.

Key Responsibilities

Contribute toRTL design and verificationof complex SoC and full-chip designs with ARM cortex M0+ , RISCV and other cores.
Develop and reviewmicro-architecture and design specifications
Implement high-quality, synthesizableRTL (Verilog/SystemVerilog)
Create and executeverification plansat block, subsystem, and full-chip levels
Develop and maintainSystemVerilog/UVM-based verification environments
Drivefunctional, code, and assertion coverage closure
Debug and resolve issues acrossdesign, integration, and full-chip bring-up
Collaborate with architecture, physical design, firmware, and validation teams
Supportclock, reset, power, and CDC/RDCdesign and verification
Mentor junior engineers and contribute to design and verification best practices
AI- Skills
- Leverage AI/ML tools to improveRTL development, verification productivity, and debug efficiency.
- Use and prompt LLM basedassistants to generate code, stimuli, documentation, root cause analysis and scripting
- Apply AI driven techniques for log analysis, waveform triage and failure clustering
- Ability to design, run, and analyzeAI‑assisted trials/experimentsto improve productivity or quality
- Know-how of integrating AI tools withexisting EDA flows and scripts.

Soft Skills

Excellent written and verbal communication skills.
Strong analytical, debugging, and problem-solving abilities.
Self-motivated, detail-oriented, and quality-focused.
Ability to collaborate effectively acrossglobal, cross-functional teams.
Comfortable working in a fast-paced, evolving MCU product environment.

Requirements/Qualifications:

Required Qualifications

Bachelor's or Master's degree inElectrical Engineering, or Electronics or VLSI
5+ years of experience inASIC/SoC design and verification
Strong expertise inRTL design using Verilog/SystemVerilog
Solid experience withSystemVerilog and C based coding
Strong understanding offull-chip SoC architecture and integration
Experience with simulation, debugging, and coverage analysis tools
Proficiency in scripting languages such asPython, Perl, or Shell
Excellent problem-solving, debugging, and communication skills

Preferred Qualifications

Experience withfull-chip integration and top-level verification
Knowledge oflow-power design and verification(UPF/CPF)
Familiarity withCDC/RDC analysis and timing concepts
Exposure toAMS or mixed-signal interfaces(e.g., PLLs, ADC/DAC)
Experience withformal verificationtechniques
Prior experience mentoring junior engineers or leading technical initiatives

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