Develops block, macro, or chip level layouts and floorplans according to project requirements, specifications, and design schematics. Applies understanding of design manuals, established processes, layout elements, and basic electronic principles to create accurate designs that meet project needs. Conducts analyses, tests, and verifies designs using different tools and techniques to identify and troubleshoot issues, and stays abreast of new verification methods. Works with multiple internal and external stakeholders to align on projects, provide updates, and resolve issues.

Minimum Qualifications:

Bachelor's degree in Electrical Engineering, Computer Science, Mathematics, Electronic Engineering, or related field and 2+ years of experience designing custom layouts in relevant domain (e.g., analog, mixed signal, RF, digital design), or related work experience.

OR

Associate's degree in Computer Science, Mathematics, Electrical Engineering or related field and 4+ years of experience designing custom layouts in relevant domain (e.g., analog, mixed signal, RF, digital design), or related work experience.

OR

High School diploma or equivalent and 6+ years of experience designing custom layouts in relevant domain (e.g., analog, mixed signal, RF, digital design), or related work experience.

2+ years of experience using layout design and verification tools (e.g., cadence, LVS, rmap).

Solid experience of 3 to 6 years in developing high speed IO/ESD/Analog layout design.

Expertise in working on FinFet layouts in lower nodes, preference to TSMCN 7nm and below.

Expertise in using the best and latest features of Cadence VXL and Calibre DRC/LVS.

Basic understanding of IO/ESD designs.

Knowledge on Basic SKILL/PERL.

Capable of working independently and with team and getting work done with contract work force.

The ability to work & communicate effectively with global engineering teams.

Senior Analog layout Engineer